1. Field of the Invention
The present invention relates to electrostatic discharge (ESD) protection devices.
2. Description of the Related Art
In a conventional ESD protection method, the I/O pins of a chip are equipped with ESD protection transistors and a PESD layer is fabricated under the drains of the ESD protection transistors. The PESD layer reduces breakdown voltage of the drains of the ESD protection transistors. Thus, for ESD protection transistors utilizing the conventional method, the drain is activated before neighboring areas, and the surfaces of the gate oxide of the ESD protection transistors are protected from being punched through by an ESD current. However, additional costs are added due to the required PESD layer, such as a mask.